This invention relates to a method for manufacturing semiconductor integrated circuit devices, and more particularly to a preferred processing method for the planarization of film that is formed to cover semiconductor wafers whose surface is uneven.
This invention can be applied to the manufacturing of semiconductor devices because it allows films with uneven surface, formed over semiconductor wafer surface, to be planarized efficiently.
Semiconductor devices are manufactured through such treatments as the doping of active impurities into the inside of semiconductor wafers, formation of various kinds of film on wafers, and etching. Recently, as semiconductor devices become more and more minute and highly integrated, surface topography of substrates under processing, which are on the way of the manufacturing process, tends to become more uneven. Therefore, planarization of the surface of substrates under processing at each step of manufacturing has come to take on great technical importance. As one example of step to planarize the film formed on a semiconductor wafer with an uneven surface in a process for the manufacturing of semiconductor devices, a metalization step will be described below with reference to FIGS. 1(a) through 1(f).
FIG. 1(a) illustrates a cross-sectional view of a wafer substrate 1 on which a first metalized layer 3 consisting of aluminum or the like is formed via a dielectric film 2. Incidentally, though not shown, a transistor part is formed on the surface of the wafer substrate 1. As an opening part is disposed in the dielectric film 2 in a connecting part between the first metalized layer 3 and the transistor, the metalized layer in that part 3 has a dent. FIG. 1(b) shows a cross-sectional view of a wafer after the completion of the metalization of a second layer. A dielectric film 4 and an aluminum film 5, which will constitute a second metalized layer, are successively formed over the first metalized layer 3 and, further, in order to make the aluminum film 5 a metalized layer having a desired pattern, which is then coated with a photo resist film 6 for exposure. Next, as shown in FIG. 1(c), using a stepper 7, the above-mentioned photo resist film 6 is exposed to light to give it a circuit pattern. During this processing, if a difference in level between a reentrant and a salient 8 on the photo resist film 6 is greater than the depth of focus of the exposure unit, no simultaneous focusing on the reentrant and the salient will be possible, inviting a serious disadvantage of defocusing.
In order to obviate the above-mentioned disadvantage, planarization of the substrate surface is performed as described below. Following the process of FIG. 1(a), as shown in FIG. 1(d), after the dielectric film 4 is formed, according to a method described later, polishing is performed to planarize the film 4 to the level indicated by reference numeral 9 in FIG. 1(d), and the state of FIG. 1(e) is there attained. Subsequently, the aluminum film 5, which will constitute the second metalized layer, and the photo resist film 6 are formed, and exposed by the stepper 7 as shown in FIG. 1(f). In this state, since the photo resist film surface is planarized, the above-mentioned disadvantage of defocusing does not arise.
FIG. 2 shows the chemical mechanical polishing (CMP) method, which has been generally used for the planarization of the above-mentioned dielectric film 4. A polishing pad 11 is attached to a platen 12 and kept rotating. This polishing pad 11 may consist of, for example, a pad that is formed by slicing polyurethane foam resin into a thin sheet, whose material and minute surface configuration may be selected according to the type of the object of polishing or the degree of desired surface roughness. On the other hand, the wafer 1 to be polished is fixed to a wafer holder 14 via a resilient backing pad 13. While rotating this wafer holder 14, the surface of the polishing pad 11 is loaded and, further by supplying a polishing slurry 15 onto the polishing pad 11, the salients of the dielectric film 4 on the wafer surface are eliminated by polishing to planarize its surface.
When a dielectric film of silicon dioxide or the like is to be polished, fumed silica is usually used as polishing slurry. Fumed silica is a suspension of minute silica particles of about 30 nm in diameter in an alkali aqueous solution such as potassium hydroxide, and it is characterized by its far higher removal rate and the smoother surface it gives with less processing damage than simple mechanical polishing with only abrasives by virtue of the additional chemical action of alkali. Such a processing method involving the supply of polishing slurry between the polishing pad and the object to be polished is well known as a free abrasive polishing technique.
FIG. 3 shows a planarization processing method using a fixed abrasive tool. This method is similar in basic hardware configuration to the free abrasive polishing technique using a polishing pad excepted that a fixed abrasive tool 16 is mounted on a rotating platen instead of the polishing pad. This process can as well be accomplished even with the supply of mere water containing no abrasives instead of fumed silica or the like as polishing liquid. Incidentally, the present inventors are studying on their own the technique that uses a fixed abrasive tool on the way of a manufacturing process for semiconductor devices, and this is no publicly known art.
This technique involves the disadvantages described below when it is applied to a practical semiconductor manufacturing process whether a polishing pad or a fixed abrasive tool is used for polishing. First, the removal rate of the polishing apparatus is too low to work on a sufficiently large number of wafers per hour (throughput). A conventional CMP apparatus with an average throughput capacity can process 20 pieces or so per hour, and this capacity is lower than those of other semiconductor manufacturing apparatuses used in other steps of the process. For this reason, when CMP apparatuses are to be introduced into the manufacturing line, a greater number of such apparatuses should be installed than otherwise to make up for their low throughput, resulting in an increased manufacturing cost. The Japanese Patent Laid-Open Publications Nos. 56-134170 and 60-25649 disclose techniques, intended to raise the throughput, to polish an object vertically fixed to allow the upper and lower exposed faces simultaneously with pieces of polishing cloth disposed above and below. However, the apparatuses disclosed in these publications are used for polishing a single material, with no consideration for the polishing of a film that is formed on a substrate with an uneven surface. Incidentally, unevenness in this context refers to a difference in level of 100 nm or more.
The poor controllability of the currently used CMP process also poses a problem in the semiconductor manufacturing process. The values of basic parameters of the process, such as the polishing rate and the within wafer and wafer to wafer uniformities of the amount of work done tend to fluctuate, and it is not easy to keep them within their respectively prescribed ranges. This mainly results from the deformation and deterioration of the surface of the polishing pad surface or fixed abrasive tool used for polishing along with the progress of processing. For this reason, every time a predetermined number of wafers have been processed, the working surface of the polishing pad or the fixed abrasive tool is revamped, which is called dressing. Usually, dressing is performed by pressing a ring having diamond abrasive on it or a disk-shaped tool against the polishing tool, and the processing tool surface is thereby restored to a state in which the polishing liquid can be readily held. Although an acceptable polishing rate can be recovered by dressing, the polishing processing tool itself wears out and becomes deformed all over while dressing is repeated over and over again, and the within wafer uniformity of the amount of work done cannot be maintained. It is because the construction of the dressing tool is not suitable for performing uniform dressing over the whole surface of the polishing pad or fixed abrasive tool, which is larger than the dressing tool. Under the present circumstances, there is the problem of difficulty to maintain the polishing rate and the planarity of the processing tool itself both at a satisfactory level.
Another reason for the difficulty to uniformize the amount of work done within the wafer is that, besides the problem with the above-mentioned dressing technique, the supply of processing liquid is uneven. Currently, the liquid used for processing is supplied from outside the wafer while it is being worked upon, resulting in a difference in supply quantity between the outer and central regions of the wafer. While the wafer diameter will tend to become larger, the larger diameter would invite a further increase in the unevenness of processing liquid supply and in the difficulty to keep the within wafer uniformity of the amount of work done. Also, in order to improve the efficiency of planarizing the wafer surface pattern, processing tools such as polishing pads that are significantly increased in hardness and in the modulus of elasticity are increasingly preferred, but harder polishing tools that yield a better planarization ability usually tend to deteriorate the within wafer uniformity, which would also make it difficult to maintain the within wafer uniformity of the amount of work done. The reason why device planarization by CMP of a wafer is especially more difficult than other polishing processes is that it is required to meet such contradictory requirements that, while only reentrants are selectively planarized at the level of pattern size on the wafer, both the chips which are reentrants and those which are salients at the level of chip size have to be uniformly polished all over the wafer surface.
Another disadvantage is an increase in the floor space the apparatus occupies. Because an increasing number of chips per wafer can reduce the production costs of semiconductor wafers, the diameter of semiconductor wafers tends to become larger. Currently, most semiconductor production facilities manufacture wafers of 200 mm in diameter as standard products, but 300 mm is likely to become a new standard diameter for wafers in the near future. On the other hand, as conventional apparatuses for the polishing process shown in FIGS. 2 and 3 would require a machining tool proportional the wafer size (approximately two to three times the diameter of the wafer) to be set horizontally, accommodating 300 mm or larger wafers which would come about in future would pose the problem that the apparatus occupies too large a floor space to be useful for practical purposes. Configurations for reducing the floor space occupied by the apparatus by vertically arranging the surface to be polished are disclosed in the Japanese Patent Laid-Open Publications Nos. 54-81591 and 4-69161. However, these apparatuses are intended for single-material polishing, but embody no consideration for the need to polish a film formed over a substrate with an uneven surface.
An object of this invention, in order to overcome the above-mentioned disadvantages of the prior art, is to provide a machining method, relating to techniques for use in the manufacturing process of semiconductor integrated circuits for the planarization of wafer surface patterns by polishing, that can accomplish planarization with excellent controllability, highly efficiently and with high qualitative stability, and that is suitable for machining larger diameter wafers as well.
The above-mentioned object to accomplish planarization with excellent controllability and stability can be achieved by a machining method using a smaller tool whose diameter is not more than twice as large as that of a wafer, and which easily permits high quality dressing and maintains planarity of its working surface. In this case, by polishing the wafer in such a matter that the whole wafer is positioned within the polishing surface of polishing tool, the amount of polishing can be controlled with high accuracy without allowing any defect to occur in the film formed over the wafer having minute asperities. Also, the disadvantage of the low removal rate can be obviated by a machining method by which the wafer is held on both sides of one wafer holder and planarization is performed simultaneously on both sides. Moreover, in order to accomplish high quality planarization, vertical positioning of a polishing tool and the working surface of the wafer holder, instead of using a conventional apparatus with a horizontally positioned polishing tool, and supplying the polishing liquid from the working surface of a polishing tool as well depending on the wafer size serves to facilitate discharging of machining dust, and to spread the polishing liquid all over the tool surface thereby to achieve uniform machining of the whole wafer surface.
As described above, according to this invention, in the polishing of semiconductor wafers, the use of a smaller-diameter machining tool within the range of d less than D less than 2d, wherein d is the wafer diameter and D is the diameter of the working surface of the machining tool, makes it easy to maintain a satisfactory degree of planarity for the machining tool, and to achieve a steady polishing rate while ensuring within wafer and wafer to wafer uniformities. Additionally, the machining tool in the polishing apparatus may have a configuration to allow replacement in accordance with the wafer size. Moreover, simultaneous machining of a plurality of wafers on both sides of the wafer holder results in an enhanced throughput of the apparatus and, further, where the machining tool is a fixed abrasive tool, dressing by scrubbing fixed abrasive tools opposite to each makes it possible to maintain a high degree of planarity for the fixed abrasive tool surface without requiring a dressing tool. Furthermore, positioning the machining tool and the wafer vertically facilitates rapid removal of foreign matter or polishing dust on the machining tool, make possible scratch-free machining and, combined with the supply of the polishing liquid from the machining tool surface, ensures uniform, supply of the machining liquid to the central part of the wafer, resulting in an enhanced within wafer uniformity of polishing.
The use of the smaller-diameter polishing tool and the vertical positioning help reduce the floor space the apparatus occupies. As a result, it contributes of space efficiency in the limited floor areas of semiconductor plants and, through the space saving, to bringing down the wafer manufacturing costs. Furthermore, if and when wafers to be machined become larger in surface area, the floor space for the apparatus in principle will not increase in proportion to the larger wafer size. Moreover, this method has an advantage in adapting to the increased wafer diameter expected in future, obviously ensuring compatibility with wafers of such a large diameter as 300 mm without needing modification of the fundamental arrangement of the apparatus.